1. Field of the Disclosure
This specification relates to a liquid crystal display (LCD) device, and particularly, to an array substrate for a fringe field switching (FFS) mode LCD device and a method for fabricating the same.
2. Background of the Disclosure
In general, liquid crystal display (LCD) devices utilize properties of liquid crystals, such as optical anisotropy and polarity. Since the liquid crystal molecules have a long thin structure and an alignment orientation, the alignment of the liquid crystal molecules can be controlled by artificial application of an electric field to the liquid crystals.
Accordingly, when the alignment orientation of the liquid crystal molecules is randomly adjusted, light is refracted toward the alignment orientation of the liquid crystal molecules due to the optical anisotropy, thereby displaying image information.
Currently, active matrix liquid crystal display (AM-LCD) devices, which have thin film transistors and pixel electrodes arranged in a matrix configuration, are being developed to have high resolution and an ability to display moving images.
The LCD device includes a color filter substrate (i.e., upper substrate) having common electrodes, an array substrate (i.e., lower substrate) having pixel electrodes, and a liquid crystal interposed between the upper and lower substrates.
The common electrode and the pixel electrodes of the LCD device drive the liquid crystal molecules by an electric field formed in an up-and-down direction. Accordingly, the LCD device has high transmittance and large aperture ratio. But the LCD device has a low viewing angle characteristic due to the liquid crystal molecules being driven by the vertically formed electric field.
Therefore, to overcome the drawback, a new technology such as a liquid crystal driving method by fringe field switching (FFS) has been proposed. The liquid crystal driving method using the FFS exhibits a high viewing angle characteristic.
Hereinafter, the related art FFS mode LCD device having the advantage will be described with reference to FIGS. 1 and 2.
FIG. 1 is a schematic planar view of an FFS mode LCD device according to the related art.
FIG. 2 is a sectional view taken along the lines IIa-IIa and IIb-IIb of FIG. 2, which schematically illustrates the array substrate for the related art FFS mode LCD device;
An array substrate 10 for an FFS mode LCD device according to the related art, as illustrated in FIGS. 1 and 2, may include a plurality of gate lines 14 extending in one direction on a transparent insulating substrate 11 and spaced from one another in parallel, a plurality of data lines 23 intersecting with the gate lines 14 to define pixel regions on the intersections, and a thin film transistor (T) disposed on each intersection between the gate lines 14 and the data lines 23 and including a gate electrode 13, an active layer 17, a source electrode 23a and a drain electrode 23b. 
A large transparent pixel electrode 29 may be disposed on an entire surface of each pixel region of the insulating substrate 11, with a space apart from the gate line 14 and the data line 23. A plurality of transparent common electrodes 35 in a shape of bar may be disposed on the pixel electrode 29 with a planarization film 31 interposed therebetween.
The pixel electrode 29 may be electrically connected to the drain electrode 23b. 
In addition, a gate pad 13a and a data pad 13b may extend from ends of the gate line 14 and the data line 23, respectively. The gate pad 13a and the data pad 13b may be connected to a gate pad connection pattern 35a and a data pad connection pattern 35b, respectively.
With the configuration, when a data signal is applied to the pixel electrode 29 via the TFT T, a fringe field may be formed between the common electrodes 35, to which a common voltage is applied, and the pixel electrode 29. Accordingly, liquid crystal molecules, which are arranged horizontally between the insulating substrate 11 and a color filter substrate (not shown) bonded to the insulating substrate 11, may be rotated by dielectric anisotropy. A rotation angle of the liquid crystal molecules may vary light transmittance through the pixel region. This may result in realizing gradation.
Hereinafter, description will be schematically given of masking processes, which are employed upon fabricating the array substrate for the related art FFS mode LCD device, with reference to FIG. 3.
FIG. 3 is a flowchart illustrating masking processes used upon fabricating the array substrate for the related art FFS mode LCD device.
As illustrated in FIG. 3, a process of fabricating the array substrate for the related art FFS mode LCD device may include a first masking process 51 of forming a gate line 14, a gate electrode 13, a gate pad 13a and a data pad 13b on an insulating substrate 11, a second masking process 52 of forming an active layer 17 on the gate electrode 13, a third masking process 53 of forming a source electrode 23a and a drain electrode 23b, which are spaced apart from each other, and the data line 23 on the active layer 17, a fourth masking process 54 of forming a drain contact hole (not shown) for exposing the drain electrode 23b, a fifth masking process 55 of forming a large pixel electrode 29, which is electrically connected to the drain electrode 23b through the drain contact hole, a sixth masking process 56 of forming a gate pad contact hole (not shown) and a data pad contact hole (not shown) for exposing the gate pad 13a and the data pad 13b, respectively, and a seventh masking process of forming common electrodes 35 corresponding to the pixel electrode 29, a gate pad connection pattern 35a and a data pad connection pattern 35b. 
On the other hand, hereinafter, description will be schematically given of a method of fabricating the array substrate for the related art FFS mode LCD device, which is fabricated through those seven-time masking processes, with reference to FIGS. 4A to 4G.
FIGS. 4A to 4G are sectional views illustrating fabricating processes of the array substrate for the related art FFS mode LCD device.
As illustrated in FIG. 4A, a plurality of pixel regions including a switching area may be defined on a transparent insulating substrate 11. A first conductive metal layer (not shown) may be deposited on a transparent insulating substrate 11 in a sputtering manner. The first conductive metal layer (not shown) may be patterned through a first masking process (not shown; see reference numeral 51 in FIG. 3) using photolithography, thereby forming a gate line (not shown; see reference numeral 14 of FIG. 1), a gate electrode 13a, which protrudes from the gate line 14, and a gate pad 13a and a data pad 13b electrically connected to an external driving circuit.
Referring to FIG. 4B, after depositing a gate insulating layer 15 on the entire surface of the substrate 11 including the gate electrode 13, an amorphous silicon layer (a-Si:H) (not shown) and an amorphous silicon layer (n+ or p+) (not shown) which contains impurities may be deposited on the gate insulating layer 15 in a sequential manner.
Afterwards, although not shown, the amorphous silicon layer (n+ or p+) containing the impurities and the amorphous silicon layer (a-Si:H) may be patterned through a second masking process (not shown; see reference numeral 52 of FIG. 3) using photolithography, thereby forming an active layer 17 and an Ohmic contact layer (not shown).
Referring to FIG. 4C, a second conductive metal layer (not shown) may then be deposited on the entire insulating substrate 11 including the active layer 17 and the Ohmic contact layer (not shown). The second conductive metal layer may be selectively patterned through a third masking process (not shown; see the reference numeral 53 of FIG. 3) using photolithography, forming a data line 23 perpendicularly intersecting with the gate line 13, and a source electrode 23a and a drain electrode 23b extending from the data line 23.
Referring to FIG. 4D, after depositing a passivation layer 25 on the entire substrate 11 including the data line 23, the passivation layer 25 may be selectively patterned through a fourth masking process (not shown; see the reference numeral 54 of FIG. 3) using photolithography, forming a drain contact hole 27 for exposing the drain electrode 23b, and a gate pad contact hole 27a and a data pad contact hole 27b for exposing the gate pad 13a and the data pad 13b, respectively.
Referring to FIG. 4E, after forming a first transparent conductive layer (not shown) on the passivation layer 25, which includes the drain contact hole 27a exposing the drain electrode 23b, the gate pad contact hole 27a and the data pad contact hole 27b exposing the gate pad 13a and the data pad 13b, the first transparent conductive layer (not shown) may be selectively patterned through a fifth masking process (not shown; see the reference numeral 55 of FIG. 3) using photolithography, forming a large pixel electrode 29 which is electrically connected to the drain electrode 23b. 
Referring to FIG. 4F, after forming a planarization layer 31 on the entire surface of the insulating substrate 11 including the pixel electrode 29, the planarization layer 31 may be patterned through a sixth masking process (not shown; see the reference numeral 56 of FIG. 3) using photolithography, forming a gate pad opening 33a and a data pad opening 33b for exposing the gate pad 13a and the data pad 13b, respectively.
Referring to FIG. 4G, after forming a second transparent conductive layer (not shown) on the planarization layer 31, which includes the gate pad opening 33a and the data pad opening 33b, the second transparent conductive layer may be selectively patterned through a seventh masking process (not shown; see the reference numeral 57 of FIG. 3) using photolithography, and forming both a plurality of diverged common electrodes 35 corresponding to the pixel electrode 29, and a gate pad connection pattern 35a and a data pad connection pattern 35b electrically connected to the gate pad 13a and the data pad 13b. Accordingly, the fabrication of the array substrate for the related art FFS mode LCD device may be completed.
Afterwards, although not shown, a color filter array substrate fabricating process and a process of forming a liquid crystal layer between the array substrate and the color filter substrate may be executed, to completely fabricate the FFS mode LCD device.
However, according to the array substrate for the FFS mode LCD device and the fabricating method thereof according to the related art, the process of forming the source electrode and the drain electrode and the process of forming the pixel electrode are separately carried out while fabricating the array substrate for the FFS mode LCD device. This may require the totally seven masking processes. Consequently, the fabricating process may become complicated and the fabricating cost may increase accordingly.
Also, according to the array substrate for the FFS mode LCD device and the fabricating method thereof according to the related art, when a structure with a common electrode on the uppermost layer is applied for low voltage driving, capacitance Cdp may change due to an overlay difference between the pixel electrode and the data line, thereby causing an even/odd defect. Especially, the even/odd defect due to the overlapping of the data line and the pixel electrode may make it difficult to apply the common electrode Vcom to the uppermost layer Top in a low power driving type.
According to the array substrate for the FFS mode LCD device and the fabricating method thereof according to the related art, since the drain contact hole has to be separately formed to electrically connect the drain electrode to the pixel electrode, an area for forming the drain contact hole is required, which may arouse a reduction of transmittance and an aperture ratio. Specifically, the requirement of the drain contact hole for forming the drain electrode and the pixel electrode may reduce an aperture plane (aperture area) that much. Also, a black matrix may further be needed to cover such drain contact hole formation area, which may result in a further reduction of the aperture plane.
Furthermore, according to the array substrate for the FFS mode LCD device and the fabricating method thereof according to the related art, since the planarization layer is formed on the entire surface of the insulating substrate, the transmittance of an opening may further be reduced.